1. Field of the Invention
The present invention relates to a method of placing dummy patterns, a semiconductor design apparatus and a semiconductor device, and particularly relates to a method of placing dummy patterns, a semiconductor design apparatus and a semiconductor device, which curb variations in the total length of the peripheries of wiring patterns and dummy patterns in a chip.
2. Description of Related Art
In recent years, semiconductor devices have been advancing toward multilayer wiring. With multilayer wiring, the high level the wiring layer is, the larger the unevenness of a plane where the wiring is formed becomes. Thus, there may occur a problem of breaking of wire and the like in a wiring layer which is formed in an upper layer. Accordingly, a technology is known of placing dummy patterns in a region where a wiring pattern is not formed and reducing the unevenness of the wiring layer in order to increase reliability in the wiring formation. This technology of placing dummy patterns is disclosed in Japanese Patent Application Laid-open No. 2000-277615.
A schematic view of a wiring region in the application is shown in FIG. 16. As shown in FIG. 16, dummy patterns 110 with low metal density are placed in blocks close to wiring patterns 100 placed in specified regions, and dummy patterns 120 with high metal density are placed away from the metal wiring. The dummy patterns uniform the density of the wiring patterns in a chip. In addition, dummy patterns with low metal density are placed in the vicinity of the wiring patterns 100. This makes it possible to reduce influence of parasitic capacity formed between the wiring patterns and the dummy patterns.
Moreover, in Japanese Patent Application Laid-open No. 2002-198435, described is a phenomenon in which the effects of a sidewall protective film for avoiding side-etching in a dry etching process decrease as the area of the sidewall of an etched film increases, and in which accordingly a CD (Critical Dimension) loss is caused. In this application, this problem is solved by adjusting the length of the peripheries of line-shaped patterns per unit area within a specified range. More specifically, described is a technology of adding rectangle- or line-shaped dummy patterns in order to adjust the length of the peripheries per unit area to within a specified range.
In semiconductor devices, making uniform a pattern density as disclosed in the first application and adjusting the length of the peripheries per unit area to within a specified range as disclosed in the second application are both matters related to etching. However, the former is caused by changes in etching rate and the latter is caused by decrease in the effects of a sidewall protective film. Their causes are different from each other, so that both of them have to be considered at the same time. However, both applications, discloses no technology taking into account these causes at the same time. Additionally, even if the method of adding dummy patterns disclosed in the first application is simply combined with the method of adding dummy patterns disclosed in the second application, the combination of the methods is not an appropriate method of adding dummy patterns. In other words, when the length of the peripheries of the dummy patterns is considered after the dummy patterns are added to uniform the pattern density, there is a possibility that the periphery length can meet the requirement but the pattern density fails. In this case, adjustments for uniforming the pattern density must further be made. Moreover, since dummy patterns are further added to the already-added dummy patterns, the dummy patterns may occupy the wiring region redundantly. In this case, for example, an attempt to make adjustments to the wiring patterns after completing the layout may result in an insufficiency in the wiring region, and this may require the whole layout to be designed again.